Method and apparatus for adjusting a performance state of a processor resource

ABSTRACT

A method, apparatus or stored program for adjusting the clock throttle rate of a central processing unit (CPU) included in a computer, in which the usage of the CPU is measured, so that the clock throttle rate of the CPU can be automatically adjusted on the measured usage of the CPU, thereby reducing the consumption of electric power without any influence on the performance of the computer.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a Continuation of U.S. patent application Ser. No. 11/589,280, filed on Oct. 30, 2006, now U.S. Pat. No. 7,702,937 and entitled Method and apparatus for Operating a Computer System By Adjusting a Performance State of a Processor Resource, which is a Continuation of U.S. Pat. application No. 09/850,059, filed May 8, 2001, now U.S. Pat. No. 7,131,016 and entitled Method and Apparatus for Adjusting Clock Throttle Rate Based on Usage of CPU, the entire disclosures of which are incorporated herein by reference.

This application claims priority to Korean Patent Application No. 25787/2000, filed May 15, 2000, the entire disclosure of which is incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a method and apparatus for adjusting the clock throttle rate of a central processing unit (CPU) included in a computer.

2. Background of the Related Art

A computer (or “system”) 4, as illustrated in FIG. 1A, is commonly used with external output devices, such as a display monitor 6 and a printer 12, as well as external input devices, such as a keyboard 8 and a mouse 10. The power management of a system 4 is often controlled by external input devices.

A power management method in the related art will be described in conjunction with FIG. 1 which illustrates a related method for managing the electric power consumed in a system. Once the system is turned on (Step S10), the system 4 determines whether a signal has been inputted from an external input device, such as a keyboard or mouse, to the system for a predetermined period of time (Step S11). If there is a signal inputted from the external input device within a predetermined period of time, the system is maintained in its ON state. On the other hand, if no signal is inputted from the external input device for the predetermined period of time, the system is switched from its ON state to an idle mode (Step S12) to reduce the electric power consumed in the system.

In systems where an advanced power management (APM) is applied, the operational mode when no signal is inputted from the external input device for a certain period of time is referred to as an “idle mode” or “doze mode”. When the system is switched to the “idle mode”, the basic input/output system (BIOS) of the system conducts an operation for reducing the clock speed supplied to the CPU and decreasing LCD brightness, etc., thereby reducing the consumption of electric power.

For instance, a dedicated power management chipset such as an Intel PIIX4E power management chipset is mainly used as a means for conducting the above mentioned APM power management operation. Typically, this power management chipset adjusts the clock throttle rate of the CPU among 7 different levels of 12.5%, 25%, 37.5%, 50%, 62.5%, 75%, and 87.5%. That is, assuming that the maximum speed of the CPU corresponds to 100%, the clock throttle rate of the CPU can be stepwise adjusted in a range from 100% to 12.5% at a reduction rate of 12.5% per step using the dedicated power management chipset (Intel PIIX4E).

In order to control the clock rate of the CPU, a clock throttle operation is also carried out by controlling desired registers of the power management chipset (Intel PIIX4E). A user controls desired registers to adjust the set-up of the BIOS to enable an idle mode supporting item and the clock rate of the CPU selects one of 7 different levels designated by the BIOS of the system, typically, 50%.

Meanwhile, in a system where an advanced configuration and power interface (ACPI) is applied and the system is in a state of use by an application program, the system sets the CPU at a clock throttle rate of 100% and the switching of the system to an “idle mode” by the BIOS of the system is not carried out. On the other hand, when the CPU is not being used by an application program, the system conducts a power management operation setting the CPU to a lower clock throttle rate.

However, the above mentioned power management methods of the related art have problems. In the case of the system to which the APM is applied, the clock throttle rate is reduced to a predetermined rate (typically, 50%) only when the system is switched from its ON state to an idle state. For this reason, there is a problem in that no power management is carried out in the ON state of the system.

Furthermore, although it is not necessary to use external input devices when operating a digital video disk (DVD) or a video file to allow the user to watch a movie or a program broadcasted on the Internet, the system should be in the ON state because the system remains in operation. In this case, however, the system may maintain or switch into the idle state because of a lack of external input by the user, thus resulting in slower or intermittent reproduction of the data.

In the case of the system to which the ACPI is applied, it is possible to conduct power management while the system is in the ON state. However, the power management is very simple, in that clocks are operated at a clock throttle rate of 100% in the operating state of the CPU, but the clocks are cut off in the non-operating state of the CPU. In accordance with such a very simple power management, clocks are supplied to the CPU at a maximum clock throttle rate even in a situation in which an application program involving a less CPU usage is used. For this reason, an increased consumption of electric power occurs unnecessarily in the system.

The above references are incorporated by reference herein where appropriate for appropriate teachings of additional or alternative details, features and/or technical background.

SUMMARY OF THE INVENTION

An object of the invention is to solve at least the above problems and/or disadvantages and to provide at least the advantages described hereinafter.

Therefore, an object of the invention is to provide a method for adjusting the clock throttle rate of a CPU in a system, in which the usage of the CPU is measured, so that the clock throttle rate of the CPU can be adjusted in a stepwise fashion, based on the measured usage of the CPU, thereby allowing the CPU to be supplied with clocks at a rate necessary for the execution of a desired program without any influence on the performance of the system, and more particularly to a method for adjusting the clock throttle rate of a CPU included in a computer, in which the usage of the CPU is measured, so that the clock throttle rate of the CPU can be automatically adjusted, based on the measured usage of the CPU, thereby reducing the consumption of electric power without any influence on the performance of the computer.

Another object of the invention is to provide a method for adjusting the clock throttle rate of a CPU in a system, in which the usage of the CPU is measured, so that the clock throttle rate of the CPU can be adjusted in a stepwise fashion, based on the measured usage of the CPU, thereby reducing the consumption of electric power.

In order to accomplish these objects, the present invention provides a method for adjusting a clock throttle rate of a central processing unit (CPU), comprising measuring a usage of the CPU, comparing the measured CPU usage with a predetermined reference CPU usage range, and adjusting the clock throttle rate of the CPU, based on a result of the comparison. The measurement of the CPU usage is carried out at every refresh time. The CPU usage is measured by calculating an idle thread value of the CPU for a predetermined period of time. The CPU usage is measured by detecting registry information of the system.

Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objects and advantages of the invention may be realized and attained as particularly pointed out in the appended claims.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention will be described in detail with reference to the following drawings in which like reference numerals refer to like elements wherein:

FIG. 1A illustrates a diagram of a computer system in the related art.

FIG. 1 is a flow chart illustrating a power management method in the related art used in a computer system;

FIG. 2 illustrates the display window of an application program for carrying out a method for adjusting the clock throttle rate of a CPU in accordance with a preferred embodiment of the present invention;

FIG. 3 is a flow chart illustrating the method for adjusting the clock throttle rate of the CPU in accordance with a preferred embodiment of the present invention; and

FIG. 4 is an architectural block diagram illustrating layers of an architecture configured in the system where a device driver is used.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

As shown in FIG. 2, the display window includes a plurality of sub-windows 20 for setting parameters required for the adjustment of the clock rate of a central processing unit (CPU), and menu bars. The sub-windows may, for example, include a sub-window “Hold Usage” representing a minimum reference usage of the CPU, a sub-window “Recov, Usage” representing a maximum reference usage of the CPU, a sub-window “CPU Usage” representing the current usage of the CPU, “Port 0x 1010h” representing an input/output register address, and “Refresh Time” representing a refresh time for refreshing the measurement of the CPU usage although other sub-windows may also be included.

In accordance with a preferred embodiment method of the present invention, desired parameters displayed on the display window are set to adjust the clock rate of the CPU at an environment setting step. For example, where the CPU usage is reduced to a value less than the minimum reference CPU usage set in the sub-window “Hold Usage” or set in a predetermined minimum reference CPU usage amount, the contents of those, which are associated with addresses 10H and 11H of input/output registers in a dedicated power management chipset (PIIX4E), that is, a register for determining a clock throttle rate and a register for enabling a clock throttle operation, are changed to reduce the clock rate of the CPU. Also, where the CPU usage is increased to a value more than the maximum reference CPU usage set in the sub-window “Recov, Usage” or set in a predetermined maximum reference CPU usage amount, the set register values are changed to increase the clock rate of the CPU. The CPU usage can be periodically measured at intervals of the refresh time set in the sub-window “Refresh Time” or at a predetermined interval of time that can be preset.

FIG. 3 is a flow chart illustrating the method for adjusting the clock throttle rate of the CPU in accordance with a preferred embodiment of the present invention. In accordance with the method illustrated in FIG. 3, when the user enables a power management setting based on a CPU clock throttle rate adjustment, it is first determined whether the refresh time has elapsed (Step S30) and if the refresh time has elapsed, the usage of the CPU is measured (Step S31). The usage of the CPU may be measured by measuring an idle thread value of the CPU for a predetermined period of time or by detecting the CPU usage from the registry information of the system.

Thereafter, the measured CPU usage is compared with the minimum reference usage and maximum reference usage previously set using the display window of FIG. 2 (Step S32) or preset values. If the measured CPU usage is less than the minimum reference usage, the clock throttle rate of the CPU is stepwise increased, thereby reducing the clock rate of the CPU (Step S34). If the CPU usage measured after the reduction of the CPU clock throttle rate is still less than the minimum reference usage, the CPU clock throttle rate is then adjusted to a next higher value, thereby further reducing the clock rate of the CPU. This procedure is repeated until the measured CPU usage is not less than the minimum reference usage.

If the measured CPU usage is between the minimum and maximum reference usages, the current clock rate of the CPU is maintained as an optimum rate (Step S33). If the measured CPU usage is more than the maximum reference usage, the clock throttle rate of the CPU is initialized (Step S35) by recovering the clock rate of the CPU to a normal rate for improving system performance. The minimum and maximum reference usages may be appropriately determined, depending on the performance of the CPU.

Since the performance and power consumption of the system may vary considerably depending on the set values of the minimum and maximum reference usages, it may be desirable for those reference values to be set by the manufacturer rather than by the user. In this connection, it may be desirable to allow the user to determine whether it is necessary to enable the power management setting.

As shown in FIG. 4, the architecture of the computer where a device driver is used includes a ring-3 layer, a ring-0 layer, and a hardware layer. The ring-3 layer is a user interface layer for enabling the clock throttle rate adjustment based on the usage of the CPU. The ring-0 layer is an intermediate layer that allows the user program to directly control the hardware layer with a device driver. When information set in the ring-3 layer is transmitted to the device driver in accordance with an input/output control of the ring-0 layer, the device driver reads the usage of the CPU, thereby controlling the dedicated power management chipset to reduce or increase the clock throttle rate of the CPU.

As apparent from the above description, the present invention provides a method of preventing degradation in the performance of a system by measuring the usage of the CPU included in the system, and appropriately controlling the clock throttle rate of the CPU based on the measured CPU usage. The present invention also reduces the consumption of electric power in the system by measuring the usage of the CPU included in the system, and appropriately controlling the clock throttle rate of the CPU based on the measured CPU usage. Additionally, where the preferred method of the present invention is applied to a notebook computer, it is also possible to extend a life time of a battery used in the notebook computer.

The foregoing embodiments and advantages are merely exemplary and are not to be construed as limiting the present invention. The present teaching can be readily applied to other types of apparatuses. The description of the present invention is intended to be illustrative, and not to limit the scope of the claims. Many alternatives, modifications, and variations will be apparent to those skilled in the art. In the claims, means-plus-function clauses are intended to cover the structures described herein as performing the recited function and not only structural equivalents but also equivalent structures. 

The invention claimed is:
 1. A method for controlling a performance state of a processor resource, the method comprising: measuring a first usage of the processor resource to determine a first measured usage; comparing the first measured usage with a first reference usage and a second reference usage, the first reference usage being higher than the second reference usage; and when the first measured usage is less than the second reference usage, performing a stepwise reduction of a clock rate, wherein the stepwise reduction of the clock rate includes (a) reducing a clock rate by a prescribed amount, (b) measuring a second measured usage based on the reduced clock rate for comparison to the second reference usage, and (c) repeating steps (a) and (b) until the second measured usage is greater than the second reference usage.
 2. The method of claim 1, wherein the first reference usage comprises a maximum reference usage and the second reference usage comprises a minimum reference usage.
 3. The method of claim 1, wherein the measuring comprises detecting processor register information.
 4. The method of claim 1, wherein the measuring comprises calculating an idle value associated with the processor resource.
 5. The method of claim 1, wherein the processor resource comprises a single central processing unit.
 6. The method of claim 1, wherein when the first measured usage is between the first and second reference usages, maintaining the clock rate.
 7. The method of claim 1, wherein when first measured usage is greater than first reference usage, the clock rate is recovered to a normal rate.
 8. A program embedded in a non-transitory machine-readable medium for implementing a method of controlling a performance state of a processor resource, the method comprising: measuring a usage of the processor resource to determine a measured usage; comparing the measured usage with a first reference usage and a second reference usage, the first reference usage being higher than the second reference usage; and when the first measured usage is less than the second reference usage, performing a stepwise reduction of a clock rate, wherein the stepwise reduction of the clock rate includes (a) reducing a clock rate by a prescribed amount, (b) measuring a second measured usage based on the reduced clock rate for comparison to the second reference usage, and (c) repeating steps (a) and (b) until the second measured usage is greater than the second reference usage.
 9. The program embedded in the non-transitory machine readable medium of claim 8, wherein the first reference usage comprises a maximum reference usage and the second reference usage comprises a minimum reference usage.
 10. The program embedded in the non-transitory machine readable medium of claim 8, wherein the measuring comprises detecting processor register information.
 11. The program embedded in the non-transitory machine readable medium of claim 8, wherein the measuring comprises calculating an idle value associated with the processor resource.
 12. The program embedded in the non-transitory machine readable medium of claim 8, wherein the processor resource comprises a single central processing unit.
 13. The program embedded in the non-transitory machine readable medium of claim 8, wherein when the first measured usage is between the first and second reference usages, maintaining the clock rate.
 14. The program embedded in the non-transitory machine readable medium of claim 8, wherein when first measured usage is greater than first reference usage, the clock rate is recovered to a normal rate. 